1. Field of the Invention
The present invention relates to the technical field of a data reproduction apparatus for reproducing digital data according to a reproduction signal that is read from a recording medium, and more particularly, to the technical field of a data reproduction apparatus that samples a reproduction signal according to a sampling clock and converts it to a sample-value series, and using a PLL (Phase Locked Loop), performs phase synchronization of the sample-value series.
2. Description of the Related Art
Recently, the use of a data reproduction apparatus, which reproduces digital data using a large-capacity, disk-shaped recording medium such as a DVD, has become popular. In this kind of data reproduction apparatus, an RF signal that corresponds to a pit line on the surface of the disk is read by a pick up, and this analog RF signal is converted to a digital sample-value series by an A/D converter. The sampling clock that is supplied to the A/D converter is necessary for synchronizing the phase of the sample-value series, so there is a PLL for detecting the phase of the sample-value series and feeding it back to the clock generator. The PLL follows the high reading speed for the recording medium, so it is preferred that the bandwidth be made as wide as possible, that is, the wider the PLL bandwidth is, the shorter the amount of time it takes to synchronize the sample-value series.
However, in the data reproduction apparatus described above, there are various delay elements in the path of the sample-value series. For example, the high-frequency emphasis circuit, processing circuits or for processing the sample values, or adaptive signal processing become delay elements. Also, when these delay factors are inserted in the PLL loop, dead time occurs and the phase margin of the PLL is reduced. Moreover, when it is not possible to maintain an adequate phase margin, it becomes difficult to increase the bandwidth of the PLL. For this kind of data reproduction apparatus with PLL, there was a problem in that widening the bandwidth of the PLL was limited by the existence of delay elements.